Design of a Hardware Architecture to Obtain the Dark Channel on Hazy Images

Abstract

The presence of large amounts of particles accumulated in the atmosphere results in low visibility in images. This effect is known as hazing. One of the most efficient methods found in the literature, which uses a single image as an input, that is, that does not require additional image information, is the Dark Channel Prior (DCP) algorithm, which is based on obtaining the dark channel to remove this effect. This paper presents the methodology and architecture in VHDL for obtaining only the dark channel on a Nexys 4 FPGA by Xilinx which can later be used to implement the DCP dehazing algorithm. The embedded system resulting from the methodology allows the images to be stored both in Flash memory and in blocks of RAM, the resulting images are displayed through the FPGA VGA port to a monitor with a resolution of 640 x 480 pixels with 12 color bits.